Ovonic Unified Memory
This Electronics Engineering Seminar Topic deals with the following:
We are now living in a world driven by various electronic equipments. Semiconductors form the fundamental building blocks of the modern electronic world providing the brains and the memory of products all around us from washing machines to super computers. Semi conductors consist of array of transistors with each transistor being a simple switch between electrical 0 and 1. Now often bundled together in there 10’s of millions they form highly complex, intelligent, reliable semiconductor chips, which are small and cheap enough for proliferation into products all around us.
Identification of new materials has been, and still is, the primary means in the development of next generation semiconductors. For the past 30 years, relentless scaling of CMOS IC technology to smaller dimensions has enabled the continual introduction of complex microelectronics system functions. However, this trend is not likely to continue indefinitely beyond the semiconductor technology roadmap. As silicon technology approaches its material limit, and as we reach the end of the roadmap, an understanding of emerging research devices will be of foremost importance in the identification of new materials to address the corresponding technological requirements.
If scaling is to continue to and below the 65nm node, alternatives to CMOS designs will be needed to provide a path to device scaling beyond the end of the roadmap. However, these emerging research technologies will be faced with an uphill technology challenge. For digital applications, these challenges include exponentially increasing the leakage current (gate, channel, and source/drain junctions), short channel effects, etc. while for analogue or RF applications, among the challenges are sustained linearity, low noise figure, power added efficiency and transistor matching. One of the fundamental approaches to manage this challenge is using new materials to build the next generation transistors.
PRESENT MEMORY TECHNOLOGY SCENARIO
As stated, revising the memory technology fields ruled by silicon technology is of great importance. Digital Memory is and has been a close comrade of each and every technical advancement in Information Technology. The current memory technologies have a lot of limitations. DRAM is volatile and difficult to integrate. RAM is high cost and volatile. Flash has slower writes and lesser number of write/erase cycles compared to others. These memory technologies when needed to expand will allow expansion only two-dimensional space. Hence area required will be increased. They will not allow stacking of one memory chip over the other. Also the storage capacities are not enough to fulfill the exponentially increasing need. Hence industry is searching for “Holy Grail” future memory technologies that are efficient to provide a good solution. Next generation memories are trying tradeoffs between size and cost. These make them good possibilities for development.
EMERGING MEMORY TECHNOLOGIES
Many new memory technologies were introduced when it is understood that semiconductor memory technology has to be replaced, or updated by its successor since scaling with semiconductor memory reached its material limit. These memory technologies are referred as ‘Next Generation Memories”. Next Generation Memories satisfy all of the good attributes of memory. The most important one among them is their ability to support expansion in three-dimensional spaces. Intel, the biggest maker of computer processors, is also the largest maker of flash-memory chips is trying to combine the processing features and space requirements feature and several next generation memories are being studied in this perspective. They include MRAM, FeRAM, Polymer Memory Ovonic Unified Memory, ETOX-4BPC, NRAM etc. One or two of them will become the mainstream.